MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 10

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
PLEASE NOTE: This manual has the following
convention:
All numerical values are shown as decimal
numbers, unless otherwise defined.
1. Functional Overview
1.1 Introduction
MT312 is a single-chip variable rate digital QPSK/
BPSK satellite demodulator and channel decoder.
The MT312 accepts base-band in-phase and
quadrature analogue signals and delivers an MPEG
or DSS packet data stream. Digital filtering in MT312
removes the need for programmable external anti-
alias filtering for all symbol rates from 1 to 45Mbaud.
Frequency, timing and carrier phase recovery are all
digital and the only feed-back to the analogue front-
end is for automatic gain control. The digital phase
recovery loop enables very fine bandwidth control
that is needed to overcome performance degradation
due to phase and thermal noise.
All acquisition algorithms are built into the MT312
controller. The MT312 can be operated in a
Command Driven Control (CDC) mode by specifying
the Symbol rate and Viterbi code rate. There is also a
provision for a search for unknown Symbol rates and
Viterbi code rates.
1.2 Analogue-to-Digital Converter
The MT312 contains dual 6-bit A/D converters which
each sample a 500mVpp single-ended analogue
input at up to 90MHz. The fixed rate sampling clock
is provided on-chip using a programmable PLL
needing only a low cost 10 to 15MHz crystal.
Different crystal frequencies can be combined with
different PLL ratios, depending on the maximum
symbol rate, allowing a flexible approach to clock
generation.
1.3 QPSK Demodulator
The demodulator in the MT312 consists of signal
amplitude offset compensation, frequency offset
compensation, decimation filtering, carrier recovery,
symbol recovery and matched filtering.
The decimation filters give continuous operation from
2Mbits/s to 90Mbits/s allowing one receiver to cover
the needs of the consumer market as well as the
single carrier per channel (SCPC) market with the
same
performance, that is, the channel reception is within
10
components
Functional Overview
without
compromising
0.5dB from theory. For a given Symbol rate, control
algorithms on the chip detect the number of
decimation stages needed and switch them in
automatically.
The frequency offset compensation circuitry is
capable of tracking out up to ±15MHz frequency
offset. This allows the system to cope with relatively
large frequency uncertainties introduced by the Low
Noise Block (LNB). Full control of the LNB is
provided by the DiSEqC™ outputs from the MT312.
Horizontal / Vertical polarisation and an instruction
modulated 22kHz signal are available under register
control.
implemented on the MT312 (ref. 2).
An internal state machine that handles all the
demodulator functions controls the signal tracking
and acquisition. Various pre-set modes are available
as well as blind acquisition where the receiver has no
prior knowledge of the received signal. Fast
acquisition algorithms have been provided for low
Symbol rate applications. Full interactive control of
the acquisition function is possible for debug
purposes.
In the event of a signal fade or a cycle slip, QPSK
demodulator allows sufficient time for the FEC to re-
acquire lock, for example, via a phase rotation in the
Viterbi decoder. This is to minimise the loss of signal
due to the signal fade. Only if the FEC fails to re-
acquire
programmable) would QPSK try to re-acquire the
signal.
The matched filter is a root-raised-cosine filter with
either 0.20 or 0.35 roll-off, compliant with DSS and
DVB standards. Although not a part of the DVB
standard, MT312 allows a roll-off of 0.20 to be used
with other DVB parameters.
An AGC signal is provided to control the signal levels
in the tuner section of the receiver and ensure the
signal level fed to the MT312 is set at an optimal
value under all reception conditions.
The MT312 provides comprehensive information on
the input signal and the state of the various parts of
the device. This information includes Signal to Noise
Ratio (SNR), signal level, AGC lock, timing and
carrier lock signals. A maskable interrupt output is
available to inform the host controller when events
occur.
lock
All
DiSEqC™
for
a
long
v2.2
period
functions
(which
are
is