MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 23

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.5.3 System Clock Frequency. Register 34 (R/W)
SYS CLK[7:0] = System clock frequency * 2 in MHz.
The SYS CLK register must be programmed to indicate the system clock frequency to the calculation unit. The
maximum system clock frequency allowed is 90MHz.
e.g. for a crystal frequency = 10MHz, if the PLL multiplication ratio is 9,
The system clock frequency = 90MHz.
Then SYS CLK[7:0] = 180.
The system clock frequency is NOT affected by the setting of SYS CLK[7:0] register.
3.6 MT312 Initialisation Read Register
3.6.1 Identification. Register 126 (R)
ID[7:0]:
SYS CLK
NAME
NAME
ID
ADR
ADR
126
34
This register provides an identification number related to the MT312 version.
B7
B7
SYS CLK[7:0] - System clock frequency x2 in MHz
B6
B6
ID[7:0] Chip identification.
B5
B5
B4
B4
B3
B3
B2
B2
Initialisation
B1
B1
B0
B0
R/W
R
MT312
hex
hex
Def
Def
00
03
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