MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 80

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
12.5 MT312 Pinout Description
80
4,5,6,7,8,11,12
46,45,44
Pin
14
16
18
19
23
26
27
28
29
32
33
34
35
38
39
40
43
47
48
49
52
Electrical Characteristics
(DISEQC2)
ADDR[7:1]
TESTCLK
DISEQC1
DISEQC0
GPP[2:0]
QSINGP
STATUS
ISINGP
RESET
MICLK
TEST1
TEST2
QREF
Name
RREF
PLL1
IREF
VRM
VRB
AGC
XTO
VRT
XTI
NC
Primary 2-wire bus address defining pins
MPEG clock input used to generate
MOCLK. Enabled when both register 96
bit 7 and register 97 bit 7 are set high. In
this mode, MICLK must be continuous.
External ADC mode clock.
Crystal clock input or external reference
clock input.
Crystal output. An internal feedback
resistor to XTI is included
Phase Locked Loop test output
ADC Voltage top reference level
I channel de-coupling input
I channel input
No connection
ADC Voltage middle reference level
Q channel input
Q channel de-coupling input
ADC Voltage bottom reference level
Bias level
For factory test only. This pin must be
connected to VSS in normal operation
For factory test only. This pin must be
connected to VSS in normal operation
AGC sigma-delta output
General Purpose Port for tuner control,
register defined.
GPP0 = secondary CLK2,
GPP1 = secondary DATA2,
GPP2 = DiSEqC™ v2.2 input signal.
DiSEqC™ Horizontal/Vertical control
DiSEqCTM 22kHz output
Active low reset input
Audio BER or Status output, register
defined
Description
I/O
I/O
I/O
23
26
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PECL
Open
Open
Note
drain
drain
state
Tri-
3.3
3.3
3.3
3.3
3.3
3.3
5
5
5
3.3
3.3
5
V
1
1
1
1
mA
3.3
1
6
6
1
1
1