MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 5

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

5.1
5.2
5.3
6
6.1
6.2
7
7.1
7.2
8
8.1
8.2
9
9.1
9.2
9.3
9.4
9.5
5
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.3.1
5.3.2
5.3.3
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2.1
6.2.2
6.2.3
6.2.4
7.1.1
7.1.2
7.1.3
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
8.1.1
8.1.2
8.2.1
8.2.2
9.5.1
9.5.2
DiSEqC Control ......................................................................................................29
Screen Printouts of DiSEqC™ Waveforms ........................................................................................ 29
DiSEqC Control Read/Write Registers ............................................................................................... 30
DiSEqC Control Read Registers ........................................................................................................ 33
QPSK demodulator ................................................................................................36
QPSK Demodulator Read/Write Registers ........................................................................................ 36
QPSK Demodulator Read Registers .................................................................................................. 42
Forward Error Correction ......................................................................................46
Forward Error Correction Read/Write Registers ................................................................................ 47
Forward Error Correction Read Registers .......................................................................................... 48
Automatic Gain Control ........................................................................................52
Automatic Gain Control Read/Write Registers ................................................................................... 52
Automatic Gain Control Read Registers ............................................................................................ 53
MPEG Packet Data Ouput .....................................................................................54
MPEG Clock Modes ........................................................................................................................... 54
Data Output Header Format - DVB only ............................................................................................ 55
MPEG/DSS Data Output Signals ....................................................................................................... 56
Data output timing .............................................................................................................................. 58
MPEG Packet Data Output Read/Write Registers ............................................................................. 59
DiSEqC™ Mode Control. Register 22 (R/W) .............................................................................. 30
DiSEqC(tm) Ratio. Register 35 (R/W) ........................................................................................ 30
DiSEqC™ Instruction (R/W). Register 36 (R/W) ........................................................................ 31
DiSEqC™ 2 Control 1. Registers 121 (R/W) .............................................................................. 31
DiSEqCTM 2 Control 2. Registers 122 (R/W) ............................................................................ 32
DiSEqC™M 2 Interrupt Indicators. Register 118 (R) .................................................................. 33
DiSEqC™M 2 Status Indicators. Register 119 (R) ..................................................................... 34
DiSEqC™ 2 FIFO. Register 120 (R) ........................................................................................... 34
Symbol Rate. Registers 23 - 24 (R/W) ....................................................................................... 36
Viterbi mode. Register 25 (R/W) ................................................................................................. 38
QPSK Control. Register 26 (R/W) .............................................................................................. 39
Go Command. Register 27 (R/W) .............................................................................................. 40
QPSK Interrupt Output Enable. Registers 28 - 30 (R/W) ........................................................... 40
QPSK STATUS Output Enable. Register 32 (R/W) .................................................................... 41
QPSK Interrupt. Registers 0 - 2 (R) ............................................................................................ 42
QPSK Status. Registers 4 - 5 (R) ............................................................................................... 44
Symbol Rate Output. Registers 116 - 117 (R) ............................................................................ 44
Monitor Registers. Registers 123 - 124 (R) ................................................................................ 45
FEC Interrupt Enable. Register 31 (R/W) ................................................................................... 47
FEC STATUS Output Enable. Register 33 (R/W) ...................................................................... 47
FEC Set Up. Register 97 (R/W) .................................................................................................. 48
FEC Interrupt. Register 3 (R) ...................................................................................................... 48
FEC Status. Register 6 (R) ......................................................................................................... 49
Measured Signal to Noise Ratio. Registers 9 - 10 (R) ................................................................ 49
Viterbi Error Count at Viterbi Input. Registers 11 - 13 (R) .......................................................... 50
Reed Solomon Bit Errors Corrected. Registers 14 - 16 (R) ........................................................ 50
Reed Solomon Uncorrected block Errors. Registers 17 - 18 (R) ................................................ 51
AGC Control. Register 39 (R/W) ................................................................................................ 52
AGC REF Reference Value. Register 41 (R/W) ......................................................................... 52
Measured Signal Level at MT312 Input. Register 19 (R) ........................................................... 53
Measured AGC Feed Back Value. Registers 108 - 110 (R) ....................................................... 53
Output Data Control. Register 96 (R/W) ..................................................................................... 59
Monitor Control. Register 103 (R/W) .......................................................................................... 59
Contents
MT312
5