MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 52

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
8 Automatic Gain Control
8.1 Automatic Gain Control Read/Write Registers
8.1.1 AGC Control. Register 39 (R/W)
B7:
B6:
B5-4:
AGC control output is a pulse density modulated output created by a sigma-delta modulator. To reduce power
consumption this is not clocked at the full system clock rate. The frequency at which this is clocked is the
system clock divided by the decimation factor in Table 6.
B3-1:
B0:
8.1.2 AGC REF Reference Value. Register 41 (R/W)
AGC REF[7:0]
The AGC loop control in MT312 is designed to bring the mean square value of the I signal (or the Q signal) at
the ADC output (prior to any digital filtering) to the value set by the AGC REF register.
52
AGC CTRL
AGC REF
NAME
NAME
Reserved.
Reserved.
AGC SD[1:0]
AGC BW[2:0]
AGC SL Analogue AGC slope
High = positive slope i.e. RF gain proportional to AGC voltage.
Low = negative slope i.e. RF gain inversely proportional to AGC voltage (default).
Automatic Gain Control
Table 4 - Sigma Delta clock decimation ratio programming
ADR
ADR
39
41
Must be set low.
Must be set low.
Sigma Delta clock decimation ratio related to system clock.
Front End AGC bandwidth (retain default value of 3).
Front End AGC reference value.
Reserved
B7
B7
AGC SD[1:0]
Reserved
B6
00
01
10
11
B6
AGC REF[7:0] AGC reference level
B5
AGC SD[1:0]
B5
B4
Decimation
B4
16
2
4
8
B3
B3
AGC BW[2:0]
B2
B2
B1
B1
AGC
B0
SL
B0
R/W
R/W
Def
hex
Def
hex
26
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