MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 40

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
6.1.4 Go Command. Register 27 (R/W)
B7-1:
B0:
If this register is read, it will return zero.
6.1.5 QPSK Interrupt Output Enable. Registers 28 - 30 (R/W)
When the bits of these three registers are set high, they enable an event to generate an interrupt on the IRQ
pin 57. All interrupts may be enabled together. These registers do not affect the indication of events in the read
registers 0 - 3.
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:
B7:
B6:
B5:
40
IE QPSK M
IE QPSK H
NAME
NAME
NAME
GO
Reserved - not used.
GO
High = Enable QPSK CT LOCK indication on interrupt pin.
High = Enable QPSK CT UNLOCK indication on interrupt pin.
High = Enable QPSK LOCK indication on interrupt pin.
High = Enable QPSK UNLOCK indication on interrupt pin.
High = Enable QPSK TS LOCK indication on interrupt pin.
High = Enable QPSK TS UNLOCK indication on interrupt pin.
High = Enable QPSK CS LOCK indication on interrupt pin
High = Enable QPSK CS UNLOCK indication on interrupt pin.
High = Enable QPSK FE AGC LOCK indication on interrupt pin.
High = Enable QPSK TS AGC LOCK indication on interrupt pin.
High = Enable QPSK TS AGC UNLOCK indication on interrupt pin.
QPSK Demodulator
ADR
ADR
ADR
27
28
29
High = release reset state to start signal capture, automatically reset to zero.
Low = no action.
B7
B7
B7
IE QPSK[15:8] Interrupt enable QPSK (middle byte)
IE QPSK[23:16] Interrupt enable QPSK (high byte)
B6
B6
B6
B5
B5
B5
Reserved
B4
B4
B4
B3
B3
B3
B2
B2
B2
B1
B1
B1
GO
B0
B0
B0
R/W
R/W
R/W
Def
hex
Def
hex
Def
hex
00
00
00