MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 22

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
3.5.2 MT312 Configuration. Register 127 (R/W)
CONFIG[7:0]: This register is for setting up the MT312. It must be loaded first before any other register. It can
only be reset by the RESET pin being pulled low.
B7:
B6-5:
Also in DSS mode TS SW RATE register (50) must be set to 20, see page 70.
B4:
B3-2:
B1:
B0:
e.g.
When MT312 is not being used it can be put into power save mode by setting bit B7 to 0.
22
CONFIG
NAME
312 EN
DSS B
0
0
1
1
If both DSS A and DSS B are set high, the MT312 will search for the code rate in DSS mode. Then
the Symbol rate is automatically set to 20Mbaud and SYM RATE registers (23 & 24) are ignored.
Also, any code rate programmed into VIT MODE register (25) and VIT SETUP register (86) will be
ignored.
BPSK
PLL FACTOR[1:0]:
B3-2
00:
01:
10:
11:
CRYS15
ADCEXT
For a crystal frequency of 10MHz, a system clock frequency of 60MHz, the PLL ratio will be 6,
requiring the PLL FACTOR[1:0] = 2.
Initialisation
ADR
127
312 EN
High = MT312 enable.
Low = MT312 disable to save power.
DSS A
0:
1:
0:
1:
High = BPSK
Low = QPSK
Multiplication factor
3
4
6
9
High = 15MHz crystal.
Low = 10MHz crystal.
High = ADC external.
Low = ADC internal.
B7
DVB mode
DSS mode 1 - code rate 2/3
DSS mode 2 - code rate 6/7
DSS search mode
DSS B DSS A
B6
B5
BPSK
B4
PLL FACTOR
B3
[1:0]
B2
CRYS
B1
15
ADC
EXT
B0
R/W
Def
hex
08