MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 60

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
Note:
B6-4:
B3-0:
I and Q input samples when MON CTRL[3:0] = 0.
DC offset in the I and Q inputs when MON CTRL[3:0] = 1.
Symbol Rate when MON CTRL[3:0] = 3, (see section 6.2.4 Monitor Registers. Registers 123 - 124 (R)).
Decimation ratio when MON CTRL[3:0] = 5, (see 6.2.4 Monitor Registers. Registers 123 - 124 (R)).
Timing synchroniser frequency lock detector value when MON CTRL[3:0] = 6, (see section 6.2.4 Monitor
Registers. Registers 123 - 124 (R)).
Timing lock detector value when MON CTRL[3:0] = 7, (see section 6.2.4 Monitor Registers. Registers 123 - 124
(R)).
Phase lock detector value when MON CTRL[3:0] = 8, (see section 6.2.4 Monitor Registers. Registers 123 - 124
(R)).
The remaining settings of MON CTRL[3:0] are either reserved for diagnostic purposes or not used.
60
the BKERR signal on pin 75 can be inverted by setting the BKERIV bit 6 of OP CTRL register 96, see
page 37.
Reserved, not used.
MON CTRL[3:0] selects which pair of registers will be read from MONITOR H & L registers 123 and
124, (see section 6.10 on page 48).
MON CTRL[3:0]
MPEG Packet Data Output
15 - 9
0
1
2
3
4
5
6
7
8
and the rest reserved
DEC RATIO[15:13]
MONITOR H (123)
MBAUD OP H
DC OFFSET I
M FLD[7:0]
CS SYM I
Reserved
Reserved
M TLD H
M PLD H
Not used
MONITOR L (124)
DC OFFSET Q
MBAUD OP L
CS SYM Q
M FLD7:0]
Reserved
Reserved
Reserved
Not used
M TLD L
M PLD L