MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 48

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
B0:
7.1.3 FEC Set Up. Register 97 (R/W)
B7:
B6:
B5:
B4:
B3:
B2:
B1-0:DS LK[1:0] + 2 =Number of bytes for de-scrambler to lose lock. The default register value of 3 is
equivalent to 5 bad sync words.
7.2 Forward Error Correction Read Registers
7.2.1 FEC Interrupt. Register 3 (R)
B7:
B6:
B5:
B4:
B3:
48
FEC SETUP
FEC INT
NAME
NAME
BER tog High = BER toggle. This bit enables the audio signal output on the STATUS pin it indicates
BER during dish alignment, see 12, section 1.4.1.2. The frequency of the signal is controlled by
VIT MAXERR register (94), see 70.
When MANUAL MOCLK (register 96 bit 7) is Low then:
DIS SR
When MANUAL MOCLK (register 96 bit 7) is High then:
DIS SR
ENCLKO
DIS DS
DIS RS
DIS VIT
EN PRS
High = DiSEqC™
High = Byte Align lock lost
High = Byte Align lockimportant indicator.
High = Viterbi lock lost
High = Viterbi lock
Forward Error Correction
ADR
ADR
97
03
High = Disable use of Symbol Rate for MOCLK generation.
Low = Use Symbol Rate for MOCLK generation.
High = Use external MICLK (pin 14) signal for MOCLK.
Low = Manually set MOCLK period from MOCLK RATIO (reg. 33).
High = Enable clock out for test purposes.
High = Disable de-scrambler.
High = Disable Reed Solomon decoder.
High = Disable Viterbi (Viterbi by pass mode)
High = Enable programmed synchronisation byte in register 98.
DIS SR
B7
B7
ENCL
KO
B6
B6
FEC INT[7:0] Interrupt FEC
DIS
DS
B5
B5
DIS
RS
B4
B4
DIS
VIT
B3
B3
PRS
EN
B2
B2
DS LK[1:0]
B1
B1
B0
B0
R/W
R
Def
hex
Def
hex
03
00