MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 47

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

7 Forward Error Correction
7.1 Forward Error Correction Read/Write Registers
7.1.1 FEC Interrupt Enable. Register 31 (R/W)
When the bits of this register are set high, they enable an event to generate an interrupt on the pin 57. All
interrupts may be enabled together.
B7:
B6:
B5:
B4:
B3:
B2:
B1:
B0:High = Enable De-scrambler lock indication on interrupt pin.
7.1.2 FEC STATUS Output Enable. Register 33 (R/W)
If more than one bit is enabled then the logical-OR combination of the selected status signals will appear on the
STATUS pin 52.
B7-4:
B3:
B2:
B1:
FEC STAT EN
IE FEC
NAME
NAME
High = Enable DiSEqC™ indication on interrupt pin.
High = Enable Byte Align lock lost indication on interrupt pin.
High = Enable Byte Align lock indication on interrupt pin.
High = Enable Viterbi lock lost indication on interrupt pin.
High = Enable Viterbi lock indication on interrupt pin.
High = Enable Viterbi BER monitor period reached indication on interrupt pin.
High = Enable De-scrambler lock lost indication on interrupt pin.
MOCLK RATIO[3:0]
DS lock
BA lock
VIT lock
ADR
ADR
31
33
B7
B7
MPEG clock ratio - 6. I.e. range is from 6 to 21
see section 9.1.3 on 54.
High = De-scrambler lock
High = Byte Align lock
High = Viterbi lock. High = Viterbi lock
MOCLK RATIO[3:0]
B6
B6
IE FEC[7:0] Interrupt enable FEC
B5
B5
B4
B4
Forward Error Correction
DS lock
B3
B3
lock
B2
B2
BA
lock
VIT
B1
B1
BER
tog
B0
B0
R/W
R/W
MT312
hex
hex
Def
Def
14
00
47