MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 69

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

10.2.32 Loss Lock Time. Register 82 (R/W)
LOSSLOCK TM (82)
LOSSLOCK TM[7:0]
After the FEC locks it can unlock due to a signal fade or a cycle slip. Then the QPSK allows the following
number of symbol periods for the FEC to regain lock :
If the FEC does not regain lock during this number of symbol periods, then QPSK will re-acquire lock.
10.2.33 Viterbi Error Period. Registers 83 - 85 (R/W)
VIT ERRPER (83, 84 & 85)
VIT ERRPER
[23:0]
10.2.34 Viterbi Set up. Register 86 (R/W)
B7-6:
B5-4:
B3-1:
B0:
VIT SETUP
NAME
LOSSLOCK TM * 262144
FR AL TM O [1:0]
SRCH CYC[2:0]
SEARCH START[2:0]
EX F LK
Viterbi error period. This is the period over which the Viterbi error count is measured. See
registers 11, 12 & 13 on page 53.
ADR
86
B7
FR AL TM
O[1:0]
Table 7 - Viterbi code rate search start
Secondary Registers for Test and De-Bugging
B6
B6-4
0
1
2
3
4
5
Default value
Default value
Frame (or byte) align time out.
Viterbi BER based search cycles.
Code rate search start, only one code rate may be selected.
Exit false lock.
SRCH CYC
B5
[1:0]
B4
Code rate search start
B3
SEARCH START
16 dec.
16,777,215 dec.FF FF FF hex.
1/2
2/3
3/4
5/6
6/7
7/8
at:
[2:0]
B2
B1
10 hex.
EX F
B0
LK
R/W
MT312
hex
Def
34
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