MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 81

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Note 1.8V tolerant pins with thresholds related to 3.3V.
1,10,20,41,51,
2,9,17,42,50,
69,68,66,65,
64,63,61,59
55,62,67
15,56,74
13,73
60,70
Pin
53
54
57
58
71
72
75
76
37
30
25
21
36
31
ADCDGND
ADCDVDD
ADCAGND
ADCAVDD
ADCFVDD
MDO[7:0]
MOSTRT
PLLVDD
MDOEN
MOCLK
BKERR
MOVAL
DATA1
CVDD
CVSS
Name
CLK1
VDD
VSS
IRQ
2-wire serial bus data
Active low interrupt output. A low output
on this pin indicates an event has
occurred and the microprocessor should
read the interrupt registers. Reading all
interrupt registers resets this pin.
MPEG clock output at the data byte rate.
MPEG transport packet data output bus.
Logic 1 = MPEG data and clock outputs
disable - Tri-state. Logic 0 = MPEG data
and clock outputs enable
MPEG data output valid. This pin is high
during the MOCLK clock cycles when
valid data bytes are being output.
Active low uncorrectable block indicator
OR no signal indicator selected by ERR
IND bit 7 of MON CTRL register.
MPEG output start signal, high on the
first byte of a packet.
Core Digital CVDD. All pins must be
connected.
Peripheral VDD. All pins must be
connected.
ADC core analogue VDD. All pins must
be connected.
ADC core digital VDD. All pins must be
connected.
ADC core front end VDD. All pins must
be connected.
PLL VDD. All pins must be connected.
Digital VSS. All pins must be connected.
Peripheral VSS. All pins must be
connected.
ADC core analogue VSS. Must be
connected to analogue GND.
ADC core digital VSS. Must be
connected to analogue GND.
2-wire serial bus clock
Description
Electrical Characteristics
I/O
I/O
O
O
O
O
O
O
I
I
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Open
Open
Note
drain
drain
state
state
state
state
state
Tri-
Tri-
Tri-
Tri-
Tri-
3.3
3.3
3.3
3.3
3.3
1.8
3.3
1.8
3.3
3.3
1.8
5
5
5
5
MT312
V
0
0
0
0
1
1
1
1
mA
6
6
1
1
1
1
1
81