MT312C ZARLINK [Zarlink Semiconductor Inc], MT312C Datasheet - Page 72

• Manufacturer Part Number: MT312C
• Description: Satellite Channel Decoder
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

MT312
10.2.48 QPSK State Control. Register 102 (R/W)
B7:
B6:
B5:
B4:
B3:
B2-0:
10.2.49 QPSK Reset. Register 104 (R/W)
B7-6:
B5:
B4:
B3:
B2:
B1:
B0:
10.2.50 QPSK Test Control. Register 105 (R/W)
QPSK TST CT (105)
QPSK TEST CTRL[7:0]
72
QPSK RESET
QPSK ST CT
NAME
NAME
Secondary Registers for Test and De-Bugging
HLD ST
AFC RS
M S RS
NXT FR
FCE ST
FORCED ST[2:0]
Reserved Must be set low.
REL QP
PR QP
PR CS
PR TS
PR FE
PR AGC
ADR
ADR
102
104
HLD
B7
ST
B7
Reserved
AFC
RS
B6
B6
High = Hold state.
High = AFC reset.
High = Mixer scan reset.
High = Get next frequency.
High = Force state.
Forced state.
High = Release QPSK FSM.
High = Partial reset FSM (applies to QPSK control).
High = Partial reset carrier synchroniser
High = Partial reset timing synchroniser (includes fine AGC).
High = Partial reset front-end logic.
High = Partial reset analogue AGC.
Default value
For factory test purposes only.
REL
M S
QP
RS
B5
B5
NXT
QP
FR
PR
B4
B4
FCE
PR
CS
B3
ST
B3
0 dec.
PR
B2
B2
TS
FORCED ST[2:0]
PR
B1
B1
FE
00 hex.
AGC
PR
B0
B0
R/W
R/W
Def
hex
Def
hex
00
00