MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 118

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clocking
19 Clocking
This section describes the PLL configuration of the MPC8572E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1
Table 76
The DDR memory controller can run in either synchronous or asynchronous mode. When running in
synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in
asynchronous mode, the memory bus is clocked with its own dedicated PLL with clock provided on
DDRCLK input pin.
118
Memory bus clock frequency
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The Memory bus clock refers to the MPC8572E memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. Refer to
e500 core processor frequency
CCB frequency
DDR Data Rate
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
Section 19.4, “DDR/DDRCLK PLL Ratio,”
at half of the DDR data rate.
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
Ratio.”
DDR data rate.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
“DDR/DDRCLK PLL Ratio,”
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically
possible via valid clock ratio setting in some condition, is not supported.
Characteristic
The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the
provides the clocking specifications for both processor cores.
Clock Ranges
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Characteristic
Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,”
Table 77
Table 76. MPC8572E Processor Core Clocking Specifications
for ratio settings.
Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,”
Table 77. Memory Bus Clocking Specifications
provides the clocking specifications for the memory bus.
Min
800
400
400
1067 MHz
for ratio settings.
1067
Max
533
667
Maximum Processor Core Frequency
Min
800
400
400
1200 MHz
Min
200
1200
Max
533
667
Min
800
400
400
1333 MHz
Max
400
1333
Max
533
667
Section 19.4, “DDR/DDRCLK PLL
Min
800
400
400
1500 MHz
MHz
Unit
Freescale Semiconductor
and
1500
Max
600
800
Section 19.4,
MHz
MHz
MHz
Unit Notes
and
1, 2, 3, 4
Notes
1, 2