MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 18

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Required assertion time of HRESET
Minimum assertion time for SRESET
PLL config input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8572E.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
RESET Initialization
For 8-bit Encoded FIFO mode:
4.6
For information on the input clocks of other functional blocks of the platform such as SerDes and eTSEC,
see the respective sections of this document.
5
Table 8
Table 9
18
PLL lock times
Local bus PLL
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 127 MHz.
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/3.2
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 167 MHz.
RESET Initialization
describes the AC electrical specifications for the RESET initialization timing.
provides the PLL lock times.
Other Input Clocks
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Parameter/Condition
Parameter/Condition
Table 8. RESET Initialization Timing Specifications
Table 9. PLL Lock Times
Symbol
—
—
Min
100
100
—
3
4
2
Min
100
50
Max
—
—
—
—
—
5
Typical
μs
μs
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
μs
μs
Max
—
—
Notes
—
2
1
1
1
1