MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 94

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in
the device is driving a 100 Ω +/–5% differential resistive load. The output eye pattern of an LP-Serial
transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need
only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized.
94
Output Voltage,
Differential Output Voltage
Deterministic Jitter
Total Jitter
Multiple output skew
Unit Interval
Output Voltage,
Differential Output Voltage
Deterministic Jitter
Total Jitter
Multiple output skew
Unit Interval
Figure 58
Characteristic
Characteristic
with the parameters specified in
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Table 69. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Table 68. Long Run Transmitter AC Timing Specifications—2.5 GBaud
V
V
J
J
S
UI
V
V
J
J
S
UI
D
T
D
T
O
DIFFPP
MO
O
DIFFPP
MO
Symbol
Symbol
Figure 70
–0.40
800
400
–0.40
800
320
Min
Min
—
—
—
—
—
—
when measured at the output pins of the device and
Range
Range
2.30
1600
0.17
0.35
1000
400
2.30
1600
0.17
0.35
1000
320
Max
Max
Volts
mV p-p
UI p-p
UI p-p
ps
ps
Volts
mV p-p
UI p-p
UI p-p
ps
ps
Unit
Unit
Voltage relative to COMMON of
Voltage relative to COMMON of
either signal comprising a
differential pair
Skew at the transmitter output
between lanes of a multilane
link
either signal comprising a
differential pair
Skew at the transmitter output
between lanes of a multilane
link
+/- 100 ppm
+/- 100 ppm
Freescale Semiconductor
Notes
Notes
—
—
—
—
—
—