MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 137

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 87
23 Document Revision History
Table 88
Freescale Semiconductor
Number
Rev.
4
3
2
explains line four of
provides a revision history for the MPC8572E hardware specification.
06/2010
03/2010
06/2009
Date
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
• In
• Updated
• In
• In
• In
• In
• In
• Clarified restrictions in
• In
• Added
• In
• In
• In
• In
• Added LPBSE to description of LGPL4/LGTA/LUPWAIT/LPBSE/LFRB signal in
• Corrected supply voltage for GPIO pins in
• Applied note to SD1_PLL_TPA in
• Updated note regarding MDIC in
• Added note for LAD pins in
• Updated
silicon.
silicon.
Table
announced in Product Bulletin #13572.
to 63% Sn, 37% Pb.
correct the package thickness and top view.
Table
changed minimum CCB clock frequency for proper PCI Express operation.
“MPC8572E Pinout Listing.”
number information. Added note indicating that silicon version 2.0 is available for prototype
purposes only and will not be available as a qualified device.
Section 22.1, “Part Numbers Fully Addressed by this Document,”
Section 18.1, “Package Parameters for the MPC8572E FC-PBGA,”
Section 18.3, “Pinout Listings,”
Section 2.1, “Overall DC Electrical
Section 22.1, “Part Numbers Fully Addressed by this Document,”
Section 3, “Power Characteristics,”
Section 4.4, “DDR Clock Timing,”
Table
Section 18.2, “Mechanical Dimensions of the MPC8572E
Section 19.1, “Clock Ranges,”
Section 19.5.2, “Minimum Platform Frequency Requirements for High-Speed Interfaces,”
4, “MPC8572E Power Dissipation.”
76, “MPC8572E Processor Core Clocking Specifications.”
Table 87. Meaning of Last Line of Part Marking
Section 14, “GPIO.”
Figure
Digit
8, “RESET Initialization Timing Specifications,” added note 2.
WW
WL
YY
Section 14.1, “GPIO DC Electrical Characteristics.”
Table
A
Table 88. Document Revision History
86, “,Part Numbering Nomenclature - Rev 1.1.1” with Rev 2.0 and Rev 2.1 part
67.
Assembly Site
E Oak Hill
Q KLM
Lot number
Year assembled
Work week assembled
Section 4.5, “Platform to eTSEC FIFO Restrictions.”
Table
updated CCB Max to 533MHz for 1200MHz core device in
Table
updated
75, “MPC8572E Pinout Listing.”
Table
Substantive Change(s)
changed DDRCLK Max to 100MHz. This change was
Description
Characteristics,” changed GPIO power from OVDD to BVDD.
updated CCB Max to 533MHz for 1200MHz core device in
75, “MPC8572E Pinout Listing.”
75, “MPC8572E Pinout Listing.”
Table
Table 75
75, “MPC8572E Pinout Listing.”
showing GPINOUT power rail as BVDD.
FC-PBGA, updated
updated
added
updated material composition
Document Revision History
Table 85
Table 86
Table
Figure 61
for Rev 2.1
for Rev 1.1.1
75,
to
137