MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 119

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following
procedures can be used:
19.2
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,
because the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock
frequency is decoupled from the CCB bus frequency.
19.3
The clock speed for each e500 core can be configured differently, determined by the values of various
signals at power up.
Freescale Semiconductor
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Start with the processor core frequency selection;
After the processor core frequency is determined, select the platform (CCB) frequency from the
limited options listed in
Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from
If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;
Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR
data rate to DDRCLK ratio from
must be greater than the platform (CCB) frequency. In other words, running DDR data rate lower
than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
SYSCLK input signal
Binary value on LA[29:31] at power up
CCB/SYSCLK PLL Ratio
e500 Core PLL Ratio
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
LA[29:31] Signals
Table 79
Binary Value of
000
001
010
011
100
101
110
111
Table 78. CCB Clock Ratio
Table
and
Table
81. Note that in asynchronous mode, the DDR data rate
80;
CCB:SYSCLK Ratio
Reserved
Reserved
10:1
12:1
4:1
5:1
6:1
8:1
Table
Table
78;
78:
Clocking
119