MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 16

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Input Clocks
At recommended operating conditions with OV
4.2
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal should be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2 × t
no minimum RTC frequency; RTC may be grounded if not needed.
4.3
Table 6
the MPC8572E.
16
At recommended operating conditions with LV
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and 60 kHz on
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies.Refer to
settings.
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK.
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for
Parameter/Condition
Real Time Clock Timing
eTSEC Gigabit Reference Clock Timing
Parameter/Condition
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Table 5. SYSCLK AC Timing Specifications (continued)
Table 6. EC_GTX_CLK125 AC Timing Specifications
Section 19.2, “CCB/SYSCLK PLL
L/TV
L/TV
DD
DD
DD
DD
=2.5V
=3.3V
/TV
of 3.3V ± 5%.
DD
of 3.3V ± 5% or 2.5V ± 5%
Symbol
t
G125R
—
Symbol
t
f
G125
G125
, t
CCB
G125F
, and minimum clock low time is 2 × t
Min
—
Ratio,” and
Min
—
—
—
Typical
Section 19.3, “e500 Core PLL
Typical
—
125
—
8
+/– 150
Max
0.75
Max
1.0
—
—
Freescale Semiconductor
Unit
MHz
ns
ns
Unit
ps
CCB
Ratio,” for ratio
. There is
Notes
—
—
1
Notes
4, 5, 6