MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 98

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial RapidIO
17.7
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the
corresponding Bit Error Rate specification
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver
Input Compliance Mask shown in
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-Ω +/– 5% differential resistive load.
17.8
Because the LP-Serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided
98
-V
-V
Receiver Eye Diagrams
Measurement and Test Requirements
V
V
DIFF
DIFF
Table 74. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
DIFF
DIFF
1.25 GBaud
2.5 GBaud
3.125 GBaud
min
max
max
min
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
0
0
Receiver Type
Figure 60. Receiver Input Compliance Mask
Figure 60
A
V
(Table 71,Table
DIFF
with the parameters specified in
min (mV) V
100
100
100
B
Time (UI)
DIFF
72, and
max (mV)
800
800
800
1-B
Table
73) when the eye pattern of the
A (UI)
0.275
0.275
0.275
1-A
Table
74. The eye pattern of
Freescale Semiconductor
B (UI)
0.400
0.400
0.400
1