MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 92

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial RapidIO
17.5
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss, S11, of the transmitter in each case shall be better than
The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential
return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components
related to the driver. The output impedance requirement applies to all valid output levels.
It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output,
in each case have a minimum value 60 ps.
It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals
that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.
92
Output Voltage,
Differential Output Voltage
Deterministic Jitter
Total Jitter
Multiple output skew
Unit Interval
Output Voltage,
Differential Output Voltage
Deterministic Jitter
Total Jitter
•
•
–10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and
–10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency
Transmitter Specifications
Characteristic
Characteristic
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Table 64. Short Run Transmitter AC Timing Specifications—1.25 GBaud
Table 65. Short Run Transmitter AC Timing Specifications—2.5 GBaud
V
V
J
J
S
UI
V
V
J
J
D
T
D
T
O
DIFFPP
MO
O
DIFFPP
Symbol
Symbol
–0.40
500
800
–0.40
500
Min
Min
—
—
—
—
—
Range
Range
2.30
1000
0.17
0.35
1000
800
2.30
1000
0.17
0.35
Max
Max
Volts
mV p-p
UI p-p
UI p-p
ps
ps
Volts
mV p-p
UI p-p
UI p-p
Unit
Unit
Voltage relative to COMMON of
Voltage relative to COMMON of
either signal comprising a
differential pair
Skew at the transmitter output
between lanes of a multilane
link
either signal comprising a
differential pair
+/- 100 ppm
Freescale Semiconductor
Notes
Notes
—
—
—
—
—
—