MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 6

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Overview
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— Three protocol engines available on a per chip select basis:
— Parity support
— Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Four enhanced three-speed Ethernet controllers (eTSECs)
— Three-speed support (10/100/1000 Mbps)
— Four IEEE Std 802.3™, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab-compatible controllers
— Support for various Ethernet physical interfaces:
— Flexible configuration for multiple PHY interface configurations
— TCP/IP acceleration and QoS features available
— Quality of service support:
— Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
— Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
— VLAN insertion and deletion
— Retransmission following a collision
— CRC generation and verification of inbound/outbound frames
— Programmable Ethernet preamble insertion and extraction of up to 7 bytes
— MAC address recognition:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– NAND Flash control machine (FCM)
– 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, RGMII and SGMII
– 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation
– Per-packet configurable acceleration
– Recognition of VLAN, stacked (Q-in-Q) VLAN, 802.2, PPPoE session, MPLS stacks, and
– Supported in all FIFO modes
– Transmission from up to eight physical queues
– Reception to up to eight physical queues
– IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
IEEE Std 802.1™ virtual local area network (VLAN) tags and priority
– Per-frame VLAN control word or default VLAN for each eTSEC
– Extracted VLAN control word passed to software separately
– Exact match on primary and virtual 48-bit unicast addresses
– VRRP and HSRP support for seamless router fail-over
ESP/AH IP-security headers
software-programmed PAUSE frame generation and recognition)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor