MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 86

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MPC8572CLPXARLD

Manufacturer Part Number
MPC8572CLPXARLD
Description
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
PCI Express
16.4.3
Table 62
specified at the component pins.
86
UI
V
T
RX-EYE
RX-DIFFp-p
Symbol
defines the specifications for the differential input at all receivers (RXs). The parameters are
Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications
Differential Receiver (RX) Input Specifications
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Unit Interval
Differential Input
Peak-to-Peak
Voltage
Minimum
Receiver Eye
Width
Parameter
Table 62. Differential Receiver (RX) Input Specifications
399.88
0.175
Min
0.4
Nominal
400
400.12
1.200
Max
Units
ps
UI
V
Each UI is 400 ps ± 300 ppm. UI does not
account for Spread Spectrum Clock
dictated variations. See Note 1.
V
See Note 2.
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as T
= 1 - T
See Notes 2 and 3.
RX-DIFFp-p
RX-EYE
= 2*|V
= 0.6 UI.
Comments
RX-D+
Freescale Semiconductor
- V
RX-D-
RX-MAX-JITTER
|

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