MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 38

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MPC8572CLPXARLD

Manufacturer Part Number
MPC8572CLPXARLD
Description
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 16
8.2.5
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn
pin (no receive clock is used in this mode, whereas for the dual-clock mode this is the PMA1 receive
clock). The 125-MHz transmit clock is applied in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in
38
At recommended operating conditions with LV
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
TBI Receive Clock 1
TBI Receive Clock 0
shows the TBI receive AC timing diagram.
(TSEC n _RX_CLK)
(TSEC n _TX_CLK)
TBI Single-Clock Mode AC Specifications
Parameter/Condition
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
RCG[9:0]
Table 32. TBI single-clock Mode Receive AC Timing Specification
Figure 16. TBI Receive AC Timing Diagram
DD
t
t
SKTRX
/TV
TRXH
t
TRDVKH
DD
of 2.5/ 3.3 V ± 5%.
t
TRX
t
TRXH
t
Valid Data
TRRH
t
t
Symbol
TRRDXKH
TRRDVKH
t
t
t
t
TRRR
TRRX
TRRJ
TRRF
/t
TRRX
t
TRXF
Valid Data
Min
7.5
2.0
1.0
40
t
TRDXKH
t
TRXR
t
TRDVKH
Typ
8.0
50
t
TRDXKH
Table
Freescale Semiconductor
Max
250
8.5
1.0
1.0
60
32.
Unit
ns
ps
ns
ns
ns
ns
%

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