HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 12

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
9.3 Register Description
9.5.3 Operation
Figure 9.27 Counter
Operation
10.1 Feature
Figure 10.1 Block Diagram of
Clock Pulse Generator
Rev. 4.00, 03/04, page xii of xlvi
Page
246
285
292
293
Revision (See Manual for Details)
Description added
Channel 3
Any Channel
Figure 9.27 amended
(Before) CMCNT0 value
(Before) CMCOR0
Figure 10.1 amended
EXTAL
5. description amended
5. Divider 2: Divider 2 generates a clock at the operating frequency
Cycle = Bcyc
CAP1
CAP2
CKIO
XTAL
DMA source address register 3 (SAR3)
DMA destination address register 3 (DAR3)
DMA transfer count register 3 (DMATCR3)
DMA channel control register 3 (CHCR3)
DMA operation register (DMAOR)
used by the bus clock (B ) and peripheral clock (P ). The
operating frequency of the peripheral clock can be 1, 1/2, 1/3, 1/4,
or 1/6 times the output frequency of PLL Circuit 1, as long as it
stays at or below the clock frequency of the CKIO pin. The
division ratio is set in the frequency control register.
oscillator
Crystal
(After) CMCOR
Clock pulse generator
PLL circuit 1
PLL circuit 2
( 1, 2, 3, 4)
( 1, 4)
(After) CMCNT value
Divider 2
Divider 1
1
1/2
1/3
1/4
1
1/2
1/3
1/4
1/6
Internal
clock (I )
Cycle = Icyc
Peripheral
clock (P )
Cycle = Pcyc
Bus clock (B )
Cycle = Bcyc