HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 39

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 22.8 Sleep to Power-On Reset STATUS Output.............................................................543
Figure 22.9 Sleep to Manual Reset STATUS Output .................................................................543
Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation) ...............545
Figure 22.11 Hardware Standby Mode Timing
Power-On Sequence......................................................................................................................570
Section 24 Electrical Characteristics
Figure 24.1 EXTAL Clock Input Timing ...................................................................................576
Figure 24.2 CKIO Clock Input Timing.......................................................................................576
Figure 24.3 CKIO Clock Output Timing ....................................................................................576
Figure 24.4 Power-On Oscillation Settling Time .......................................................................577
Figure 24.5 Oscillation Settling Time at Standby Return (Return by Reset)..............................577
Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI) ...............................577
Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL) ...................578
Figure 24.8 PLL Synchronization Settling Time by Reset or
Figure 24.9 PLL Synchronization Settling Time at the returning from Standby mode
Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication
Figure 24.11 Reset Input Timing ................................................................................................581
Figure 24.12 Interrupt Signal Input Timing................................................................................581
Figure 24.13 IRQOUT Timing ...................................................................................................581
Figure 24.14 Bus Release Timing...............................................................................................582
Figure 24.15 Pin Drive Timing at Standby .................................................................................582
Figure 24.16 Basic Bus Cycle (No Wait) ...................................................................................585
Figure 24.17 Basic Bus Cycle (One Wait)..................................................................................586
Figure 24.18 Basic Bus Cycle (External Wait)...........................................................................587
Figure 24.19 Burst ROM Bus Cycle (No Wait)..........................................................................588
Figure 24.20 Burst ROM Bus Cycle (Two Waits)......................................................................589
Figure 24.21 Burst ROM Bus Cycle (External Wait) .................................................................590
Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD
Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD
Figure 24.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
Figure 24.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read
Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD
Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD
Figure 24.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write
(Return by IRQ/IRL Interrupt).................................................................................579
NMI at the returning from Standby mode (Return by Reset or NMI).....................578
RCD
RCD
RCD
(When CA Goes Low during WDT Operation on Standby Mode Cancellation) ..546
Rate Modified .......................................................................................................579
0, CAS Latency
1, CAS Latency
0, TPC
1, TRWL = 0) .............................................................................597
1, TPC
3, TPC
1)...................................................................593
0)...................................................................594
0, CAS Latency 1, TPC
2, CAS Latency 2, TPC
0, TPC
2, TPC
Rev. 4.00, 03/04, page xxxix of xlvi
0, TRWL = 0) .............595
1, TRWL = 1) .............596
4),
4),
4),
0)....591
1)....592