HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 438

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes
2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4. After the end of serial transmission, the SCK0 pin is held in the high state.
Figure 14.20 shows an example of SCI transmit operation.
Rev. 4.00, 03/04, page 392 of 660
that the SCTDR contains new data and loads this data from the SCTDR into the SCTSR.
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to
1, the SCI requests a transmit-data-empty interrupt (TXI) at this time.
If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external
clock source is selected, the SCI outputs data in synchronization with the input clock. Data are
output from the TxD0 pin in order from the LSB (bit 0) to the MSB (bit 7).
data from the SCTDR into the SCTSR, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, transmits the MSB, then holds the
transmit data pin (TxD0) in the MSB state. If the TEIE in the SCSCR is set to 1, a transmit-end
interrupt (TEI) is requested at this time.
Synchronization
Serial data
TDRE
TEND
TXI interrupt
clock
generated
request
Transfer direction
Figure 14.20 Example of SCI Transmit Operation
Bit 0
LSB
with the TXI interrupt
Writes data to TDR
processing routine
and clears TDRE
bit to 0
Bit 1
1 frame
TXI interrupt
MSB
Bit 7
generated
request
Bit 0
Bit 1
Bit 6
TEI interrupt
generated
request
Bit 7