HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 141

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

IRL Interrupts
IRQ Pin Interrupts
On-Chip Peripheral Module Interrupts
H-UDI Interrupt
Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level
and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR
at the time the interrupt is accepted is saved to SSR. The code corresponding to the
IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as
H'200 + B' (IRL3–IRL0)
and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is
not set in the interrupt mask bit of SR. See section 6, Interrupt Controller (INTC), for more
information.
Conditions: IRQ pin is asserted and the interrupt mask bit of SR is lower than the IRQ
priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction
boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the
interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are
set to 1 and a branch occurs to VBR + H'0600. The received level is not set to the interrupt
mask bit of SR. See section 6, Interrupt Controller (INTC), for more information.
Conditions: The interrupt mask bit of SR is lower than the on-chip peripheral module
(TMU, RTC, SCI0, SCI2, A/D, LCDC, PCC, DMAC, WDT, REF) interrupt level and the
BL bit in SR is 0. The interrupt is accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the
interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are
set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC),
for more information.
Conditions: H-UDI interrupt command is input (see section 21.4.4, H-UDI Interrupt) and
the interrupt mask bit of SR is lower than 15 and the BL bit in SR is 0. The interrupt is
accepted at an instruction boundary.
Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The
SR at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and
INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR +
H'0600. See section 6, Interrupt Controller (INTC), for more information.
H'20. See table 6.4 for the corresponding code. The BL, MD,
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