HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 428

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 14.11 shows an example of SCI receive operation in the asynchronous mode.
14.4.2
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Rev. 4.00, 03/04, page 382 of 660
Example: 8-bit data with parity and one stop bit
RDRF
Serial
FER
data
Multiprocessor Communication
1
Start
bit
0
D 0
D 1
1 frame
Data
Figure 14.11 SCI Receive Operation
request generated
D 7
RXI interrupt
Parity
bit
0/1
Stop
bit
1
processing routine
Start
and clears RDRF
the RXI interrupt
0
Reads data with
bit
bit to 0
D 0
D 1
Data
D 7
Parity
request generated
bit
0/1
by framing error
ERI interrupt
Stop
bit
1
(marking)
1
Idling