HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 187

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2.8
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the
break conditions of channel B.
Bit
15 to 8
7
6
5
4
3
2
Break Bus Cycle Register B (BBRB)
Bit Name
—
CDB1
CDB0
IDB1
IDB0
RWB1
RWB0
Initial Value
All 0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. These bits are
always read as 0.
CPU Cycle/DMAC Cycle Select B
Select the CPU cycle or DMAC cycle as the bus
cycle of the channel B break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle
Instruction Fetch/Data Access Select B
Select the instruction fetch cycle or data access
cycle as the bus cycle of the channel B break
condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle
Read/Write Select B
Select the read cycle or write cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write
or data access cycle
cycle
Rev. 4.00, 03/04, page 141 of 660