HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 211

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an
external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on
reset. The correspondence between the external pins (MD4 and MD3) and memory size is listed in
table below.
Table 8.3
For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control
register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used. When the
synchronous DRAM interface is used, word or longword can be chosen as the bus width.
When the PCMCIA interface is used, set the bus width to byte or word. When synchronous
DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When
using port A or B, set a bus width of 8 or 16 bits for all areas. For more information, see section
8.4.2, Bus Control Register 2 (BCR2).
Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond
to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0
addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the
address space obtained by adding to it H'20000000
which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000
space is reserved, so do not use it.
8.3.1
This LSI supports PCMCIA standard interface specifications in physical space areas 5 and 6
(except for WP).
The interfaces supported are basically the "IC memory card interface" and "I/O card interface"
stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1).
MD4
0
0
1
1
PCMCIA Support
Correspondence between External Pins (MD4 and MD3) and Memory Size
n–H'1FFFFFFF + H'20000000
MD3
0
1
0
1
Memory Size
Reserved (Setting prohibited)
8 bits
16 bits
32 bits
n (n 0 to 7) corresponding to the area 7 shadow
n (n
1 to 6). The address range for area 7,
Rev. 4.00, 03/04, page 165 of 660