HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 84

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: * The normal number of execution cycles is shown. The value in parentheses is the number
Table 2.7 lists the logic operation instructions.
Table 2.7
Note:
Rev. 4.00, 03/04, page 38 of 660
Instruction
SUB
SUBC
SUBV
Instruction
AND
AND
AND.B #imm,@(R0,GBR)
NOT
OR
OR
OR.B
TAS.B @Rn*
TST
TST
TST.B #imm,@(R0,GBR)
XOR
XOR
XOR.B #imm,@(R0,GBR)
of cycles required in case of contention with the preceding or following instruction.
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
Rm,Rn
#imm,R0
Rm,Rn
#imm,R0
* The on-chip DMAC's bus cycle is not inserted between the read and write cycles of the
TAS instruction. The bus authority is not released by the BREQ.
Logic Operation Instructions
Operation
Rn–Rm
Rn–Rm–T
Borrow
Rn–Rm
Underflow
Operation
Rn & Rm
R0 & imm
(R0 + GBR) & imm
(R0 + GBR)
~Rm
Rn | Rm
R0 | imm
(R0 + GBR) | imm
(R0 + GBR)
If (Rn) is 0, 1
1
Rn & Rm; if the result
is 0, 1
R0 & imm; if the result
is 0, 1
(R0 + GBR) & imm;
if the result is 0, 1
Rn ^ Rm
R0 ^ imm
(R0 + GBR) ^ imm
(R0 + GBR)
MSB of (Rn)*
T
Rn
Rn,
T
Rn,
Rn
T
T
Rn
Rn
R0
Rn
R0
R0
T;
Code
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
T
Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
0100nnnn00011011
0010nnnnmmmm1000
11001000iiiiiiii
11001100iiiiiiii
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Privileged
Mode
—
—
—
Privileged
Mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cycles T Bit
1
1
1
Cycles T Bit
1
1
3
1
1
1
3
4
1
1
3
1
1
3
—
Borrow
Underflow
—
—
—
—
—
—
—
Test
result
Test
result
Test
result
Test
result
—
—
—