HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 197

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3.6
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and
2. The branch address before branch occurs can be calculated from the address and the pointer
3. The branch address before branch occurrence, IA, has different values due to some kinds of
4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the
The PC value is the start address of the instruction that follows the instruction already executed
when break processing started up. When a data value is added to the break conditions, the
place where the break will occur cannot be specified exactly. The break will occur before the
execution of an instruction fetched around the data access where the break occurred.
interrupt) is generated, the address from which the branch source address can be calculated and
the branch destination address are stored in BRSR and BRDR, respectively. The branch
address and the pointer, which corresponds to the branch, are included in BRSR.
stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR),
and IA (the instruction address before branch occurs) is as follows: IA = BSA – 2 * PID.
Notes are needed when an interrupt (a branch) is issued before the branch destination
instruction is executed. In case of the next figure, the instruction “Exec” executed immediately
before branch is calculated by IA = BSA – 2 * PID. However, when branch “branch” has delay
slot and the destination address is 4n + 2 address, the address “Dest” which is specified by
branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA – 2 * PID is not
applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied
only to this case and then some cases are classified as follows:
Exec:branch Dest
Dest:instr
Int: interrupt routine
If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions
in this table are accounted for it. Therefore, the true branch source address is calculated with
BSA and PID values stored in BRSR.
branch.
a. Branch instruction
b. Interrupt
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read
BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR,
longword access should be used. Also, the PC trace has a trace pointer, which initially points
to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of
The branch instruction address
The last instruction executed before interrupt
The top address of interrupt routine is stored in BRDR.
PC Trace
interrupt
(not executed)
Rev. 4.00, 03/04, page 151 of 660