HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 169

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.4.3
The interrupt control register 1 (ICR1) is a 16-bit register that specifies the detection mode to
external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level.
Bit
15
14
13
12
11
10
Bit Name
MAI
IRQLVL
BLMSK
—
IRQ51S
IRQ50S
Interrupt Control Register 1 (ICR1)
Initial Value
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Mask All Interrupts
When set to 1, masks all interrupt requests when a
low level is being input to the NMI pin. Masks NMI
interrupts in standby mode.
0: All interrupt requests are not masked when a low
1: All interrupt requests are masked when a low level
Interrupt Request Level Detect
Selects whether the IRQ3 to IRQ0 pins are used as
four independent interrupt pins or as 15-level interrupt
pins encoded as IRL3 to IRL0.
0: Used as four independent interrupt request pins
1: Used as encoded 15-level interrupt pins as IRL3 to
BL Bit Mask
Specifies whether NMI interrupts are masked when
the BL bit of the SR register is 1.
0: NMI interrupts are masked when the BL bit is 1
1: NMI interrupts are accepted regardless of the BL
Reserved
This bit is always read as 0. The write value should
always be 0.
IRQ5 Sense Select
Select whether the interrupt signal to the IRQ5 pin is
detected at the rising edge, at the falling edge, or at
low level.
00: An interrupt request is detected at IRQ5 input
01: An interrupt request is detected at IRQ5 input
10: An interrupt request is detected at IRQ5 input low
11: Reserved (Setting prohibited)
level is being input to the NMI pin
is being input to the NMI pin
IRQ3 to IRQ0
IRL0
bit setting
falling edge
rising edge
level
Rev. 4.00, 03/04, page 123 of 660