HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 439

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Receiving Serial Data (Clock Synchronous Mode): Figure 14.21 shows a sample flowchart for
receiving serial data. Serial data reception should be carried out in the procedure described below
after setting the SCI in a reception-enabled state. When switching from the asynchronous mode to
the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or
FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled.
1. Receive error processing: If a receive error occurs, read the ORER bit in
2. SCI status check and receive data read: Read the SCSSR, check that RDRF is
3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the
Figure 14.21 Sample Flowchart for Serial Data Receiving
No
SCSSR to identify the error. After executing the necessary error processing,
clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1.
set to 1, then read receive data from the SCRDR and clear RDRF to 0. The RXI
interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
frame MSB (bit 7) of the current frame is received.
No
Read receive data in SCRDR and
clear RDRF bit in SCSSR to 0
Clear RE bit in SCSCR to 0
Read ORER bit in SCSSR
Read RDRF bit in SCSSR
All data received?
Start reception
End reception
ORER = 1?
RDRF = 1?
No
Yes
Yes
Yes
No
Clear ORER bit in SCSSR to 0
Overrun error processing
Error processing
ORER = 1?
Rev. 4.00, 03/04, page 393 of 660
End
Yes