HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 151

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.3.2
Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The
LRU is updated.
Read Miss: An external bus cycle starts and the entry is updated. The way replaced is shown in
table 5.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the
miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU
in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0
and the V bit is set to 1.
Legend
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
31
Virtual address
MMU
Read Access
Physical address
Entry selection
Figure 5.2 Cache Search Scheme (Normal Mode)
12 11
255
CMP0 CMP1 CMP2 CMP3
0
1
V U Tag address
Hit signal 1
4 3 2 1 0
Ways 0 to 3
Longword (LW) selection
LW0
Rev. 4.00, 03/04, page 105 of 660
LW1
LW2
Ways 0 to 3
LW3