ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 126

• Manufacturer Part Number: ATTINY48-PU
• Description: MCU AVR 4K ISP FLASH 1.8V 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5
14.5.1
126
Register Description
ATtiny48/88
SPCR – SPI Control Register
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize. This is clearly seen by summarizing
and
Table 14-2.
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
marized below:
Table 14-3.
Bit
0x2C (0x4C)
Read/Write
Initial Value
CPOL
Table 14-4 on page
0
0
1
1
CPOL
Setting SPI Mode using Control Bits CPOL and CPHA
CPOL Functionality
0
1
SPIE
R/W
7
0
CPHA
Figure 14-3
0
1
0
1
127, as done in
SPE
R/W
6
0
and
SPI Mode
DORD
R/W
5
0
Figure 14-4
0
1
2
3
Leading Edge
Table 14-2
MSTR
Falling
Rising
R/W
4
0
for an example. The CPOL functionality is sum-
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
CPOL
Setup (Rising)
below.
R/W
3
0
CPHA
R/W
2
0
SPR1
R/W
Table 14-3 on page 126
1
0
Trailing Edge
Falling
Rising
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing eDge
Setup (Rising)
SPR0
R/W
0
0
8008G–AVR–04/11
SPCR