ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 199

MCU AVR 4K ISP FLASH 1.8V 28-DIP

ATTINY48-PU

Manufacturer Part Number
ATTINY48-PU
Description
MCU AVR 4K ISP FLASH 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY48-PU

Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Package
28PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY48-PU
Manufacturer:
ATMEL
Quantity:
5 530
Part Number:
ATTINY48-PU
Manufacturer:
AVX
Quantity:
30 000
21.2.11
21.2.12
8008G–AVR–04/11
Programming the Lock Bits
Reading Fuse and Lock Bits
Figure 21-5. Programming the FUSES Waveforms
The algorithm for programming the lock bits is as follows (see
194
Lock bits can only be cleared by executing Chip Erase.
The algorithm for reading fuse and lock bits is as follows (see
194
Fuse and lock bit mapping is illustrated in
RESET +12V
• A: Load command “0010 0000”
• C: Load data low byte. Bit n = “0” programs the Lock bit. If LB1 and LB2 have been
• Give WR a negative pulse and wait for RDY/BSY to go high
• A: Load command “0000 0100”
• Set OE to “0”, BS2 to “0” and BS1 to “0”. Low fuse bits can now be read at DATA (“0” means
• Set OE to “0”, BS2 to “1” and BS1 to “1”. High fuse bits can now be read at DATA (“0” means
• Set OE to “0”, BS2 to “1”, and BS1 to “0”. Extended fuse bits can now be read at DATA (“0”
• Set OE to “0”, BS2 to “0” and BS1 to “1”. Lock bits can now be read at DATA (“0” means
• Set OE to “1”
RDY/BSY
programmed, it is not possible to program the Lock Bits by any External Programming mode
programmed)
programmed)
means programmed)
programmed)
PAGEL
for details on command and data loading):
for details on command loading):
CLKI
DATA
XA1
XA0
BS1
BS2
WR
OE
0x40
A
DATA
C
Write Fuse Low byte
XX
0x40
A
Figure
DATA
C
21-6, below.
Write Fuse high byte
XX
“Programming the Flash” on page
“Programming the Flash” on page
0x40
A
ATtiny48/88
DATA
C
Write Extended Fuse byte
XX
199

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