ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 134

• Manufacturer Part Number: ATTINY48-PU
• Description: MCU AVR 4K ISP FLASH 1.8V 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

134
ATtiny48/88
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 15-8. Arbitration Between Two Masters
Note that arbitration is not allowed between:
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
Synchronized
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
SCL Line
SDA from
SDA from
Master A
Master B
SDA Line
START
Arbitration, SDA
Master A Loses
A
SDA
8008G–AVR–04/11