ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 50

• Manufacturer Part Number: ATTINY48-PU
• Description: MCU AVR 4K ISP FLASH 1.8V 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

50
ATtiny48/88
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Table 8-1.
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler Bits 3, 2, 1 and 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 8-2 on page
Table 8-2.
WDTON
WDP3
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
WDP2
WDE
0
0
0
0
1
1
1
1
0
0
Watchdog Timer Configuration
Watchdog Timer Prescale Select
X
0
0
1
1
50.
WDP1
0
0
1
1
0
0
1
1
0
0
WDIE
X
0
1
0
1
WDP0
0
1
0
1
0
1
0
1
0
1
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt & System Reset Mode
System Reset Mode
1024K (1048576) cycles
WDT Oscillator Cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
Number of
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
Typical Time-out at
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
= 5.0V
8008G–AVR–04/11