ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 140

• Manufacturer Part Number: ATTINY48-PU
• Description: MCU AVR 4K ISP FLASH 1.8V 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Assembly Code Example
Transmission Modes
ATtiny48/88
in
andi r16, 0xF8
cpi
brne ERROR
ldi
out
ldi
(1<<TWEN)
out
wait2:
in
sbrs r16,TWINT
rjmp wait2
in
andi r16, 0xF8
cpi
brne ERROR
ldi
out
ldi
(1<<TWEN)
out
wait3:
in
sbrs r16,TWINT
rjmp wait3
in
andi r16, 0xF8
cpi
brne ERROR
ldi
(1<<TWINT)|(1<<TWEN)|
out
r16,TWSR
r16, START
r16, SLA_W
TWDR, r16
r16, (1<<TWINT) |
TWCR, r16
r16,TWCR
r16,TWSR
r16, MT_SLA_ACK
r16, DATA
TWDR, r16
r16, (1<<TWINT) |
TWCR, r16
r16,TWCR
r16,TWSR
r16, MT_DATA_ACK
r16,
(1<<TWSTO)
TWCR, r16
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
C Example
if ((TWSR & 0xF8) != START)
TWDR = SLA_W;
TWCR = (1<<TWINT) |
(1<<TWEN);
while (!(TWCR & (1<<TWINT)))
if ((TWSR & 0xF8) !=
MT_SLA_ACK)
TWDR = DATA;
TWCR = (1<<TWINT) |
(1<<TWEN);
while (!(TWCR & (1<<TWINT)))
if ((TWSR & 0xF8) !=
MT_DATA_ACK)
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO);
ERROR();
;
ERROR();
;
ERROR();
Comments
Check value of TWI Status
Register. Mask prescaler bits. If
status different from START go to
ERROR
Load SLA_W into TWDR
Register. Clear TWINT bit in
TWCR to start transmission of
address
Wait for TWINT Flag set. This
indicates that the SLA+W has
been transmitted, and
ACK/NACK has been received.
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_SLA_ACK go to ERROR
Load DATA into TWDR Register.
Clear TWINT bit in TWCR to
start transmission of data
Wait for TWINT Flag set. This
indicates that the DATA has been
transmitted, and ACK/NACK has
been received.
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_DATA_ACK go to ERROR
Transmit STOP condition
8008G–AVR–04/11