ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 213

• Manufacturer Part Number: ATTINY48-PU
• Description: MCU AVR 4K ISP FLASH 1.8V 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 2-Wire/I2S/SPI
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Package: 28PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.9
8008G–AVR–04/11
SPI Characteristics
See
Table 22-8.
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 22-4
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
1. In SPI Programming mode the minimum SCK high/low period is:
2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-
- 2 t
- 3 t
tion of other AVR microcontrollers manufactured in the same process technology.
SPI Timing Parameters
CLCL
CLCL
and
for f
for f
(1)
Figure 22-5
CK
CK
< 12 MHz
> 12 MHz
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
for details.
Min
4 • t
2 • t
10
t
20
20
ck
ck
ck
Typ
See
50% duty cycle
3.6
10
10
0.5 • t
10
10
15
15
10
Table 14-5
sck
ATtiny48/88
Max
1600
213
ns