ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 195
ATTINY48-PU
Manufacturer Part Number
ATTINY48-PU
Description
MCU AVR 4K ISP FLASH 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-PU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Package
28PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY48-PU
Manufacturer:
ATMEL
Quantity:
5 530
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Part Number:
ATTINY48-PU
Manufacturer:
AVX
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8008G–AVR–04/11
D. Load Data High Byte
E. Latch Data
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
G. Load Address High byte
H. Program Page
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
3. Give CLKI a positive pulse. This loads the data byte.
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the data byte.
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the address high byte.
1. Give WR a negative pulse. This starts programming of the entire page of data.
2. Wait until RDY/BSY goes high (See
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give CLKI a positive pulse. This loads the command, and the internal write signals are
While the lower bits in the address are mapped to words within the page, the higher bits
address the pages within the FLASH. This is illustrated in
that if less than eight bits are required to address words in the page (pagesize < 256), the
most significant bit(s) in the address low byte are used to address the page when performing
a Page Write.
waveforms)
RDY/BSY goes low.
reset.
Figure 21-3
for signal waveforms).
Figure 21-2 on page
Figure 21-3
ATtiny48/88
for signal
196. Note
195
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