Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 149

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

PS026308-1207
OCD Serial Errors
Breakpoints
Runtime Counter
The On-Chip Debugger detects any of the following error conditions on the DBG pin:
•
•
•
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long serial break back to the host, and resets the auto-baud
detector/generator. A framing error or transmit collision may be caused by the host
sending a serial break to the OCD. As a result of the open-drain nature of the interface,
returning a serial break back to the host only extends the length of the serial break if the
host releases the serial break early.
The host transmits a serial break on the
F083A Series devices or when recovering from an error. A serial break from the host
resets the auto-baud generator/detector, but does not reset the OCD control register. A
serial break leaves the device in DEBUG mode, if that is the current mode. The OCD is
held in reset until the end of the serial break when the DBG pin returns high. Because of
the open-drain nature of the DBG pin, the host sends a serial break to the OCD even if the
OCD is transmitting a character.
Execution breakpoints are generated using the BRK instruction (Opcode
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If breakpoints are
enabled, the OCD enters DEBUG mode and idles the eZ8 CPU. If breakpoints are not
enabled, the OCD ignores the BRK signal and the
instruction.
Breakpoints in Flash Memory
The
byte in Flash memory. To implement a breakpoint, write
overwriting the current instruction. To remove a breakpoint, the corresponding page of
Flash memory must be erased and reprogrammed with the original data.
The On-Chip Debugger contains a 16-bit runtime counter. It counts system clock cycles
between breakpoints. The counter starts counting when the On-Chip Debugger leaves
DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches
the maximum count of
Serial break (a minimum of nine continuous bits low)
Framing error (received
Transmit collision (simultaneous transmission by OCD and host detected by the OCD)
BRK
instruction is Opcode
FFFFH
Stop
.
00H
bit is low)
, which corresponds to the fully programmed state of a
DBG
pin when first connecting to the Z8 Encore!
BRK
instruction operates as an NOP
00H
Z8 Encore!
to the required break address
Product Specification
®
On-Chip Debugger
00H
F083A Series
). When the
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