Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 75

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 43. IRQ2 Enable Low Bit Register (IRQ2ENL)
Table 44. Interrupt Edge Select Register (IRQES)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Interrupt Edge Select Register
Shared Interrupt Select Register
7
IES7
R/W
R/W
0
7
0
Reserved—Must be 0.
C3ENL—Port C3 interrupt request enable low bit
C2ENL—Port C2 interrupt request enable low bit
C1ENL—Port C1 interrupt request enable low bit
C0ENL—Port C0 interrupt request enable low bit
The interrupt edge select (IRQES) register determines whether an interrupt is generated
for the rising edge or falling edge on the selected GPIO Port A or Port D input pin. See
Table
IESx—Interrupt edge select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input or PDx.
where x indicates the specific GPIO port pin number (0 through 7).
The shared interrupt select (IRQSS) register determines the source of the PADxS
interrupts. See
Port A and alternate sources for the individual interrupts.
44.
6
IES6
R/W
R/W
0
6
0
Reserved
Table 45
5
IES5
R/W
R/W
0
5
0
on page 64. The shared interrupt select register selects between
4
IES4
R/W
R/W
0
4
0
FCDH
FC8H
3
C3ENL
IES3
R/W
R/W
0
3
0
2
C2ENL
IES2
R/W
R/W
Z8 Encore!
0
2
0
Product Specification
1
C1ENL
IES1
R/W
R/W
0
1
0
®
Interrupt Controller
F083A Series
0
C0ENL
IES0
R/W
R/W
0
0
0
63