Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 69

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Interrupt Control Register Definitions
PS026308-1207
Caution:
Caution:
Caution:
Software Interrupt Assertion
Interrupt Request 0 Register
Program code generates interrupts directly. Writing 1 to the correct bit in the interrupt
request register triggers an interrupt (assuming that interrupt is enabled). When the
interrupt request is acknowledged by the eZ8 CPU, the bit in the interrupt request register
is automatically cleared to 0.
The interrupt control registers enable individual interrupts, set interrupt priorities and
indicate interrupt requests for all the interrupts other than the Watchdog Timer interrupt,
the primary oscillator fail trap, and the Watchdog oscillator fail trap interrupts.
The interrupt request 0 (IRQ0) register stores the interrupt requests for both vectored and
polled interrupts. See
controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
To avoid missing interrupts, use the following coding style to clear bits in the interrupt
request 0 register:
The coding style listed below that generates software interrupts by setting bits in the
interrupt request registers is not recommended. All incoming interrupts received
between execution of the first
To avoid missing interrupts, use the following coding style to set bits in the interrupt
request registers:
Good coding style that avoids lost interrupt requests:
Poor coding style that results in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
Table 32
on page 58. When a request is sent to the interrupt
LDX
command and the final
Z8 Encore!
LDX
Product Specification
command are lost.
®
Interrupt Controller
F083A Series
57