Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 94

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 54. Timer 0–1 Control Register 1 (TxCTL1)
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
TEN
R/W
7
0
TMODEHI—Timer mode high bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. For more
details, see
TICONFIG—Timer interrupt configuration
This field configures timer interrupt definition.
PWMD—PWM delay value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their active state.
•
•
•
•
•
•
•
•
INPCAP—Input Capture event
This bit indicates whether the most recent timer interrupt is caused by a timer input
Capture event.
Timer 0–1 Control Register 1
The timer 0–1 control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
0x = Timer interrupt occurs on all the defined reload, compare and input events.
10 = Timer interrupt occurs only on defined input Capture/Deassertion events.
11 = Timer interrupt occurs only on defined Reload/Compare events.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
0 = Previous timer interrupt is not caused by timer input Capture event
1 = Previous timer interrupt is caused by timer input Capture event
TPOL
R/W
6
0
Timer 0–1 Control Register 1
R/W
5
0
PRES
R/W
4
0
F07H, F0FH
on page 82.
R/W
3
0
R/W
Z8 Encore!
2
0
Product Specification
TMODE
R/W
1
0
®
F083A Series
R/W
0
0
Timers
82