Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 85

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

PS026308-1207
5. Write to the timer reload high and low byte registers to set the reload value (PWM
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
7. Configure the associated GPIO port pin for the timer output and timer output
8. Write to the timer control register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
If an initial starting value other than
registers, the ONE-SHOT mode equation determines the first PWM time-out period.
If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is
represented by:
PWM Output High Time Ratio (%)
If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is
represented by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate
external timer input transition occurs. The capture count value is written to the timer
PWM high and low byte registers. The timer input is the system clock. The TPOL bit in
the timer control register determines if the capture occurs on a rising edge or a falling edge
of the timer input signal.
When the Capture event occurs, an interrupt is generated and the timer continues counting.
The INPCAP bit in TxCTL1 register is set to indicate the timer interrupt because of an
input Capture event.
PWM Output High Time Ratio (%)
PWM Period (s)
duration of the negative phase of the PWM signal (as defined by the difference
between the PWM registers and the timer reload registers).
period). The reload value must be greater than the PWM value.
to the relevant interrupt registers.
complement alternate functions. The timer output complement function is shared with
the timer input function for both timers. Setting the timer mode to dual PWM, will
automatically switch the function from timer-in to timer-out complement.
=
--------------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value
0001H
=
=
Reload Value PWM Value
----------------------------------------------------------------------- -
Prescale
--------------------------------- -
Reload Value
PWM Value
is loaded into the timer high and low byte
Reload Value
–
Z8 Encore!
100
Product Specification
®
F083A Series
100
Timers
73