Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 46
Z8F083ASJ020EG
Manufacturer Part Number
Z8F083ASJ020EG
Description
IC ENCORE XP MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F083ASJ020EG.pdf
(256 pages)
Specifications of Z8F083ASJ020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
256 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
269-4558-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F083ASJ020EG
Manufacturer:
Zilog
Quantity:
363
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HALT Mode
Peripheral Level Power Control
Power Control Register Definitions
PS026308-1207
Power Control Register 0
Executing the eZ8 CPU HALT instruction places the device into HALT mode. In HALT
mode, the operating characteristics are:
•
•
•
•
•
•
•
The eZ8 CPU is brought out of HALT mode by any one of the following operations:
•
•
•
•
•
To minimize current in HALT mode, all GPIO pins that are configured as digital inputs
must be driven to VDD when pull-up register bit is enabled or to one of power rail (VDD
or GND) when pull-up register bit is disabled.
In addition to the STOP and HALT modes, it is possible to disable each peripheral on each
of the Z8 Encore! F083A Series devices. Disabling a given peripheral minimizes its power
consumption.
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
Primary oscillator is enabled and continues to operate.
System clock is enabled and continues to operate.
eZ8 CPU is stopped.
Program counter (PC) stops incrementing.
WDT’s internal RC oscillator continues to operate.
If enabled, the WDT continues to operate.
All other on-chip peripherals continue to operate.
Interrupt
WDT time-out (interrupt or reset)
POR
VBO reset
External RESET pin assertion
Z8 Encore!
Product Specification
®
Low-Power Modes
F083A Series
34
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