Z8F083ASJ020EG Zilog, Z8F083ASJ020EG Datasheet - Page 93

• Manufacturer Part Number: Z8F083ASJ020EG
• Description: IC ENCORE XP MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F083ASJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4672 - KIT DEVELOPMENT F083A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4558-5

Table 53. Timer 0–1 Control Register 0 (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
Table 51. Timer 0–1 PWM High Byte Register (TxPWMH)
Table 52. Timer 0–1 PWM Low Byte Register (TxPWML)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS026308-1207
Timer 0–1 Control Registers
TMODEHI
R/W
R/W
R/W
7
0
7
0
7
0
PWMH and PWML—Pulse width modulator high and low bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the timer control register (TxCTL1).
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in capture or CAPTURE/COMPARE modes.
Time 0–1 Control Register 0
The timer control register 0 (TxCTL0) and timer control register 1 (TxCTL1) determine
the timer operating mode. It also includes a programmable PWM deadband delay, two bits
to configure timer interrupt definition, and a status bit to identify, if the most recent timer
interrupt is caused by an input Capture event.
R/W
R/W
R/W
6
0
6
0
6
0
TICONFIG
R/W
R/W
R/W
5
0
5
0
5
0
Reserved
R/W
R/W
R/W
4
0
4
0
4
0
F04H, F0CH
F05H, F0DH
F06H, F0EH
PWMH
PWML
R/W
R/W
R/W
3
0
3
0
3
0
PWMD
R/W
R/W
R/W
Z8 Encore!
2
0
2
0
2
0
Product Specification
R/W
R/W
R/W
1
0
1
0
®
1
0
F083A Series
INPCAP
R/W
R/W
R/W
0
0
0
0
Timers
0
0
81